CLK_IN input frequency must be in the range 5 to 60 MHz. Out of this range, the performances may be decreased. In case of multi-cameras synchronization (means more than one camera on one acquisition board):
? the "master" camera will provide DATA, STROBE and LVAL signals to the acquisition board. The others will only provide DATA.
? the external clock CLK_IN must be input on each cameras to guaranty perfect data synchronization.
? the trigger(s) input (TRIG1 and/or TRIG2) must be input on each cameras. It is recommended to synchronize the rising edge of these signals on the CLK_IN falling edge.
? cables must be balanced between each cameras (same quality, same length) to ensure perfect cameras synchronization.
? the CLK_IN frequency must be equal to the two CCD register frequency. It means that the user shall use either H=2 (2 taps at CLK_IN data rate) or H=10 (1 tap at 2xCLK_IN data rate). Using H=1 clock mode will provide LVAL jitter on the "slave" camera.
? Only "triggered and integration time controlled" (M=3 or M=4) can be used. These modes ensure perfect readout phase starting for each cameras.
1 Power Supply It is recommended to insert a 1A fuse between the power supply and the camera. I = input, O = output, I/O = bidirectional signal, P = power/ground, NC = not connected 9.2 Camera Control The Camera Link interface provides four LVDS signals dedicated to camera control (CC1 to CC4). On the AViiVA, three of them are used to synchronize the camera on external events. I = input, O = output, I/O = bidirectional signal, P = power/ground, NC = not connected Note: CC3 is not used. 9.3 Video Data Data and enable signals are provided on the Camera Link interface. I = input, O = output, I/O = bidirectional signal, P = power/ground, NC = not connected Table 9-1. Power Supply Signal Name I/O Type Description PWR P – DC power input: +12V to +24V (±0.5V) GND P – Electrical and Mechanical ground Table 9-2. Camera Control Signal Name I/O Type Description TRIG1 I RS644 CC1 – Synchronization input (refer to “Synchronization Mode” on page 6) TRIG2 I RS644 CC2 – Start Integration period in dual synchro mode (refer to “Synchronization Mode” on page 6) CLK_IN I RS644 CC4 – External clock for (multi-)camera synchronization (refer to “Synchronization Mode” on page 6) Table 9-3. Video Data Signal Name I/O Type Description ODD[11-0] O RS644 Odd pixel data (refer to “Output Data Timing” on page 8), ODD-00 = LSB, ODD-11 = MSB EVEN[11-0] O RS644 Even pixel data (refer to “Output Data Timing” on page 8), EVEN-00 = LSB, EVEN-11 = MSB STROBE O RS644 Output data clock (refer to “Output Data Timing” on page 8), data valid on the rising edge LVAL O RS644 Line valid (refer to “Output Data Timing” on page 8), active